The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 1990

Filed:

Sep. 01, 1989
Applicant:
Inventor:

Tamas S Szepesi, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 21 ; 323282 ; 323285 ; 363 79 ; 363 97 ;
Abstract

A circuit (20, 40, 50, 60) for generating an optimal compensating ramp voltage signal V.sub.cramp, with the minimum necessary slope, m.sub.c for a current mode DC/DC converter is shown. The adaptive compensating ramp generating circuit (20) is comprised of two voltage dividers (22, 24), the first voltage divider 22 divides an input voltage V.sub.IN and the second voltage divider 24 divides an output voltage V.sub.OUT. The first voltage divider (22) has two resistors (26, 28) in series: the first resistor (26) has a resistance of (1/B-1) * R ohms and the second resistor (28) has a resistance of R ohms. V.sub.OUT is divided by the second voltage divider (24) having two resistors (29, 30) in series: the first resistor (29) has a resistance of (1/A-1) * R ohms and the second resistor (30) has a resistance of R ohms. The constants A, B, and C are selected for the particular type of DC/DC converter employed. The divided voltages A * V.sub.OUT and B * V.sub.IN are input into a voltage controlled current source (32). The voltage controlled current source (32) has a scaling resistor R.sub.scale, an amplifier (36), a transistor Q, and a diode D1. The output of the current source (38) is coupled to a capacitor C.sub.ramp whose voltage realizes the slope of the compensating ramp signal, V.sub.cramp. The capacitor C.sub.ramp is charged through R.sub.scale.


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