The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 1990
Filed:
Apr. 12, 1989
Satoru Ogihara, Hitachi, JP;
Shunichi Numata, Hitachi, JP;
Kunio Miyazaki, Hitachi, JP;
Takashi Yokoyama, Hitachi, JP;
Ken Takahashi, Ibaraki, JP;
Tasao Soga, Hitachi, JP;
Kazuji Yamada, Hitachi, JP;
Hiroichi Shinohara, Hitachi, JP;
Hideo Suzuki, Katsuta, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor chip module includes semiconductor chips each of which has contacts on its entire front face. A multi-layered organic circuit board having a small dielectric constant is provided for mounting the semiconductor chips. Intermediate ceramic substrates having the same thermal expansion coefficient as that of the semiconductor chip, are also provided. Each such intermediate ceramic substrate has contacts on its front and back faces corresponding to those of the semiconductor chip. These contacts are electrically connected directly in a one-to-one relationship. The contacts on the semiconductor chip and the corresponding ones on the front face of the intermediate ceramic substrates are connected by solder. The contacts on the back face of the intermediate ceramic substrate and the corresponding contacts on the front face of the multi-layered ceramic circuit board are connected by respective conductive pins having a predetermined flexibility and rigidity through a predetermined gap therebetween. With this arrangement, the relative displacement due to a thermal expansion difference between the intermediate ceramic substrate and the multi-layered organic circuit board is permitted without causing substantial stress thereon.