The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 1990
Filed:
Oct. 28, 1987
Richard C Eden, Thousand Oaks, CA (US);
John E Clark, Newbury Park, CA (US);
Alan S Fiedler, Thousand Oaks, CA (US);
Frank S Lee, Thousand Oaks, CA (US);
Robert Miller, Newbury Park, CA (US);
Gigabit Logic, Newbury Park, CA (US);
Abstract
A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called 'V.sub.BB -Feedback' uses 'zero translation delay' direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an 'extra' V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the 'extra' V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the 'extra' V.sub.BB input. ECL compatability is accomplished by combining a reasonably compliant, but uniform, CDFL voltage shifter with feedback circuitry to maintain the shift voltages at proper levels thereby achieving the desired input logic threshold.