The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 1990
Filed:
Mar. 15, 1989
Applicant:
Inventors:
Kiichi Yamashita, Kanagawa, JP;
Keiichi Kitamura, Kokubunji, JP;
Nobuo Kotera, Kokubunji, JP;
Yasushi Hatta, Kodaira, JP;
Hiroyuki Tanaka, Fuchu, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307362 ; 307443 ; 307448 ; 307450 ; 3073032 ;
Abstract
A logic circuit made up of FET's is disclosed in which an output interface circuit is formed of a source follower circuit including a signal transmitting FET and a constant-current supplying FET, and a ratio of the gate width of the signal transmitting FET to the gate width of the constant-current supplying FET is set so that the high and low levels of the output signal of the logic circuit are independent of the threshold voltage of the FET's.