The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 1990
Filed:
Aug. 03, 1989
Applicant:
Inventors:
Stephen L Smith, Tempe, AZ (US);
Dean Mueller, Chandler, AZ (US);
Assignee:
Motorola Inc., Schaumburg, IL (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307469 ; 307451 ; 307465 ;
Abstract
A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.