Synchronizer for establishing synchronization between data and clock

Abstract

A frame synchronizer comprises a frame sync detector for detecting a frame sync pattern multiplexed with a data signal. First and second counters are incremented in response to an input clock signal to generate output signals at frame intervals. A mismatch detector detects a first mismatch between the output of sync detector and the output of first counter and a second mismatch between the sync detector output and the output of second counter. To reduce resynchronization period, the second counter is disabled in response to the detection of the second mismatch and its binary count is loaded into the first counter upon detection of the first mismatch. According to a different aspect, a bit synchronizer includes a plurality of latches connected to a data input terminal for respectively latching a data signal in response to a latch timing signal applied thereto. A mismatch detector is provided for detecting a mismatch between outputs of the latches. The detection of the mismatch indicates that data and clock inputs has lost bit synchronization and the latch timing pulse is approaching a data transition. Clock input is normally applied from an input terminal to the latches as the latch timing signal. Upon detection of a mismatch, the phase, or logic level of the latch timing signal is reversed to shift is timing to a point where the data signal has a steady logic level.