Digital signal fault detector

Abstract

The present invention comprises an electrical test circuit for testing a signal in a digital circuit, to detect common analog signal deficiencies or 'faults'. More specifically, the test circuit can simultaneously detect one or all of three such faults in a digital circuit, including: (1) a voltage spike which occurs when the signal briefly jumps either high or low; (2) a float fault which occurs when the signal is floating for too long; and (3) a noise fault which occurs when the signal passes from either the high or the low state to the float state, and then returns directly to the same state. The signal to be tested is first processed in an input state discriminator to classify it by state, either high, low, or float. In a preferred embodiment, both the high voltage threshold and the low voltage threshold of the input state discriminator are adjustable separately to accommodate all logic families. Following classification, three circuits test simultaneously for the appearance of the three separate faults, each circuit testing for a different fault. The spike fault circuit and the float fault circuit each include an adjustable timer, logic, and a comparator to test for the respective fault. The noise fault circuit includes logic to test for a noise fault. Thus, the present invention is adaptable for testing virtually any digital circuit, operating asynchronously or at any of a wide variety of frequencies. The present invention can be used alone as a device to verify proper digital circuit operation, or it can be used in combination with another testing device such as a logic analyzer.