The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 1990

Filed:

Aug. 07, 1989
Applicant:
Inventor:

Charles H Ng, Sunnyvale, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 364488 ; 364489 ; 364490 ;
Abstract

In the present disclosure, a method of routing interconnections between a semiconductor module and another semiconductor module in a planar field by the use of a digital computer program is disclosed. The method is a variation of the prior art YACR method. The method provides for variable width track routing, as well as cost equation for net assignment and cost equation of net chosen to particular a horizontal track. The present invention also relates to a method for positioning the modules. The method of positioning the two modules or compacting the modules is a method for moving tracks between modules from one module to the other module as close to the opposite module as possible within the design rule constraints. The tracks are then moved in an opposite direction and the straightest segment to minimize jogs is chosen. Each track is then moved in the opposite direction and is moved as close to the straightest previous adjacent track as possible, within the design rule constraint.


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