The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 1990
Filed:
Oct. 30, 1989
Friedrich A Karner, Milton, VT (US);
Douglas W Phelps, Jr, Burlington, VT (US);
Stephen G Starr, Essex Junction, VT (US);
William C Ward, Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A plastic encapsulated semiconductor package in which the connecting lead frame members are deposited over the surface of the device together with a covering ground plane so as to provide enhanced electrical and thermal coupling of the members and the device and so reduce the signal to noise ratio by a factor or greater than three over that available in other similar plastic encapsulated packages while simultaneously improving the transfer of heat out of the package. In particular, a lead frame having a plurality of conductors is attached to a major active surface of a semiconductor chip via a ground plane which, in the preferred embodiment, is a multilayered structure containing an insulated integral, uniform ground plane positioned between the lead frame and the chip and adhesively and insulatively joined to both of them. Wires connect terminals on the major active surface of the semiconductor chip to the ground plane and to selective lead frame conductors. The lead frame, the ground plane structure, the semiconductor chip, and the wires which connect the semiconductor chip terminals to the ground plane and to selected lead frame conductors are encapsulated with a suitable insulating material to form a semiconductor module or package.