Bi-cmos clock driver with reduced crossover current

Abstract

The present circuit is intended for use in providing CCD phase clocks. It has the benefit of reduced crossover currents which in turn reduces power consumption and device size requirements. The circuit is comprised of a pair of folded cascode CMOS amplifier input stages, a pair of bipolar output stages containing vertical NPN transistors, and 2 PMOS sense transistors for each output stage for reducing the crossover current which occurs when switching output stages. These sense transistors reduce the power consumption of the circuit and the size of the transistors necessary for the output. The input stage has the capability of operating from TTL or ECL signal inputs by selecting an input reference voltage. The folded cascode configuration also provides the level shifting necessary for inputs to the output stage's NPN transistors. The sense transistors provide feedback in the form of the charge stored in the output transistors to prevent a pair of output transistors from turning on prior to the other pair turning off.