Method of fabricating semiconductor devices with sub-micron linewidths

Abstract

Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces. The implantation profile's spatial variation with respect to the dielectric spacer dimension can be engineered to fabricate a lightly doped drain (LDD) MESFET. Finally, a Microwave Enhancement Depletion Integrated Circuit (MEDIC) process sequence mixes low threshold voltage digital MESFETs with higher threshold voltage microwave MESFETs.