High speed digital carry look ahead circuit for parallel adder

Abstract

A digital IC carry look ahead circuit consists of a carry transfer stage (12) and a logic network (10). The carry transfer stage transfers the carry from a preceding stage to a next following stage unless altered by its associated logic network which provides symmetrical outputs. The logic network comprises two or more half adders connected sequentially between a common node (38) in the carry transfer state and a voltage supply line (50). Each half adder includes first, second and third active switching devices (K.sub.i, G.sub.i and P.sub.i). The third active switching device (P.sub.i) are connected in series between the common node (38) and the voltage supply line (50). The first and second active switching device (K.sub.i, G.sub.i) of each half adder are connected in series and with a common junction thereof connected to a common junction of its associated third active device and the next following third active device or the connection to the voltage supply line (50). Corresponding free terminals of the first and second switching devices constitute symmetrical outputs of the logic network. The first switching devices are activated in response to A.sub.i *B.sub.i =1 where A.sub.i and B.sub.i are bits of corresponding significance of two numbers added. The second switching devices are activated in response to A.sub.i +B.sub.i =1 and the third switching devices are activated in response to A.sub.i .sym.B.sub.i =1.