Write buffer for a digital processing system

Abstract

The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a 'smart' buffer. The write buffer has multiple buffer locations for storing data received from a central processor, a data merger for merging data designated by the central processor for subsequent storage in contiguous memory locations, and a write controller for selectively writing the data from the plurality of write buffer locations to the memory. The system further includes time stamp registers in communication with the write controller for storing and updating a time signal representative of the write buffer location having most recently received data. The controller is responsive in part to the time signal, and inhibits the writing to memory of the data in the write buffer location having most recently received data since this is the location most likely to be eligible for a data merge. This feature decreases the number of interruptions to the CPU for data transfer operations.