The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 1990
Filed:
Nov. 09, 1987
Applicant:
Inventors:
Peng-Huat Ang, Los Altos, CA (US);
Charles C Stearns, Palo Alto, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364754 ; 364736 ;
Abstract
Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.
Ang, Peng-Huat. (1990). Digital multiplier circuit and a digital multiplier-accumulator circuit (U.S. Patent No. 4958312). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4958312
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile