System with a n stages timing silo and p stages information silo for

Abstract

A method and arrangement for siloing information in a computer system uses a smaller number of large-size latches by providing a timing silo having a set of n timing state devices sequentially connected for receiving and siloing at least one bit. The arrangement has an information silo having a set of p information state devices which are sequentially connected for receiving and siloing information. These information state devices have device enables coupled to separate locations in the timing silo so that a bit at a particular location in the timing silo enables the information state device which is coupled to that particular location. In this arrangement, the number of p information state devices is less than the number n of timing state devices. Less large-size latches are therefore needed. The invention also finds use in the resetting of a control module in processor after a trap by providing a timing silo which keeps track of the number of addresses which have been generated within the trap shadow. Upon receiving a signal that a trap has occurred, a total number of addresses generated within the trap shadow is indicated by the timing silo and a uniform stride is subtracted from a current address until the trap causing address is reached. By this arrangement, a large number of large-size latches are not needed to silo all of the virtual addresses which are in the trap shadow. Instead, only one bit needs to be siloed in the timing silo since the addresses have a uniform stride.