The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 1990

Filed:

Jun. 27, 1989
Applicant:
Inventors:

Noriyuki Honma, Kokubunji, JP;

Tohru Nakamura, Tanashi, JP;

Kazuo Nakazato, Kokubunji, JP;

Motoaki Matsumoto, Kokubunji, JP;

Tetsuya Hayashida, Nishitama, JP;

Masaharu Kubo, Hachioji, JP;

Kazuhiko Sagara, Suginami, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 34 ; 357 36 ; 357 49 ; 357 59 ; 357 67 ; 357 72 ; 357 88 ; 357 92 ;
Abstract

A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.


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