The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 1990
Filed:
Dec. 30, 1988
Robert H Bullis, Avon, CT (US);
James L Swindal, East Hampton, CT (US);
Walter J Wiegand, Jr, Glastonbury, CT (US);
Charles B Brahm, Ellington, CT (US);
Harold D Meyer, South Windsor, CT (US);
United Technologies Corporation, Hartford, CT (US);
Abstract
Pressure sensors utilizing capacitance variations to sense pressure variations of the silicon-on-silicon type in which dielectric drift, which occurs in such sensors due to the changing characteristics primarily of the dielectric wall support layer (16) extending up from the silicon substrate (12) between it and the silicon diaphragm (11), is minimized by in turn minimizing the contribution of the dielectric layer to the total capacitance of the sensor (10), reducing the dielectric contribution of the capacitance from, for example, about fifty (50%) percent down to a range of no more than about twenty to twenty-five (20-25%) percent and down typically to sixteen to about ten (16%-10%) percent of the total capacitance or lower. Three exemplary approaches are illustrated, namely, etching the outer edges of the dielectric layer, making the wall(s) it form(s) thinner (FIG. 2); reducing the horizontal thickness of the effective peripheral, lower edge(s) of the silicon diaphragm where it interfaces in contact with the wall(s) formed by the dielectric layer (FIG. 3); and/or reducing the horizontal thickness of the effective peripheral, upper edge(s) of the silicon base or substrate where it interfaces with the wall(s) formed by the dielectric layer (FIUG. 4); and/or a combination of one or more of these approaches or any other approach that minimizes the effective capacitive contribution of the peripheral dielectric layer to the total capacitance of the sensor and hence to long term drift.