Clock recovery and hold circuit for digital tdm mobile radio

Abstract

A clock recovery circuit for a digital TDM mobile radio transceiver is disclosed. In the 'acquisition mode', a first phase-locked loop is configured to acquire synchronization with the input data signal, and a second phase-locked loop is coupled to the first PLL's output signal, thereby providing the recovered clock signal. The controller monitors the transmit control line and the received signal strength so as to switch the clock recovery circuit into a second configuration during a TDM transmit burst or a received signal fade. In this 'hold mode', the second PLL is configured to free-run within a specified tolerance, while the first PLL is coupled to the second PLL's output signal. The controller maintains this 'hold' configuration until the received signal is again present, and until the first PLL again acquires synchronization to the input data signal. In this manner, the controller prevents the recovered clock signal from losing bit synchronization or phase synchronization during transmit bursts, during the transmit-to-receive synthesizer out-of-lock period, or during Rayleigh fades. The present invention is particularly adapted for use in a TDM system utilizing 0.2 GMSK modulation, wherein there is less apparent clock signal available for clock recovery.