The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 1990

Filed:

Feb. 28, 1989
Applicant:
Inventor:

Yasuo Kobayashi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523003 ; 36523006 ;
Abstract

A semiconductor memory device having improved address wiring and address decoding structures is disclosed. The memory device comprises a plurality of address decoders arranged separately, an address buffer for generating 'n'-bits of address signals, a set of address wirings coupled to said address buffer and the address decoders, the number of address wirings being 'n', and a plurality of inverting circuits provided for the address decoders, each of inverting circuits coupled to the address wirings and being responsive to the signals at the address wirings for generating their complementary signals to be applied to the associated address decoder.


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Kobayashi, Yasuo. (1990). Semiconductor memory device with improved address wiring arrangement (U.S. Patent No. 4953134). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4953134

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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