Multiplier circuit with selectively interconnected pipelined multipliers

Abstract

A multiplier which processes 32 bit operands to provide two 16 bit by 16 bit fixed point products or one 32 bit floating point product during each clock pulse. Two 16 bit by 16 bit fixed point products or one 32 bit floating point product are initiated on every clock pulse and results of the multiplication process are available after a fixed pipeline delay on a continuous basis. The fixed and floating point pipeline operations may also be interleaved. The 32 bit input operands are selected from three external sources or from the last output product. A modified Booth algorithm is implemented employing dual parallel processing paths which are employed to separately produce the 16 bit by 16 bit fixed point products or are combined to produce the 32 bit floating point product. Exponent computations are performed in parallel in the floating point computational mode.