Software configurable memory architecture for data processing system

Abstract

A graphics data processing system memory is allocatable by software between system memory and graphics framebuffer storage. The memory comprises two-port elements connected in parallel from the RAM port to a controller connected to a bus, and having serial output ports connected to output circuitry to map the storage to a display. Corresponding locations, relative to element origin, in all elements are addressed in parallel as an array. Three modes of memory transactions are all accomplished as array accesses. First, a processor reads/writes the system memory portion by a combination of parallel array access and transfers between controller and bus in successive bus cycles. Second, the controller executes atomic graphics operations on the framebuffer storage using successive array accesses; third, the processor can read/write a framebuffer pixel, by an array access of framebuffer storage with masking of unaddressed pixels. An interface arbitrates among requests for memory access.