Semiconductor memory device with first and second word line drivers

Abstract

A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.