The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 1990

Filed:

Aug. 25, 1988
Applicant:
Inventor:

Shigeki Matsuoka, Suita, JP;

Assignee:

Ricoh Company, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364787 ;
Abstract

An adder has first through third switching circuits, a logic circuit and an adding circuit part. The first switching circuit is coupled between a carry bit input terminal and a carry bit output terminal. The second switching circuit is coupled between a first power source voltage and the carry bit output terminal, and the third switching circuit is coupled between a second power source voltage and the carry bit output terminal. The logic circuit controls the ON/OFF states of the first through third switching circuits so that only one switching circuit is turned ON responsive to two binary values which are to be added in the adding circuit part. The propagation time of a carry bit signal from the carry bit input terminal to the carry bit output terminal is constant regardless of the number of bits of the adding circuit part.


Find Patent Forward Citations

Matsuoka, Shigeki. (1990). Adder having means for reducing propagation time of carry bit (U.S. Patent No. 4949297). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4949297

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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