The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 1990
Filed:
Mar. 31, 1987
Fernando W Arraut, San Diego, CA (US);
Laszlo V Gal, Poway, CA (US);
Robert C Shen, San Diego, CA (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.