The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 1990
Filed:
Oct. 28, 1988
Applicant:
Inventor:
Seiji Ueda, Ohtsu City, JP;
Assignee:
Matsushita Electronics Corporation, Kadoma, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437195 ; 437193 ; 437192 ; 437 49 ; 148D / ;
Abstract
Disclosed is a process for making a semiconductor device which has two polycrystalline layers (5) and (15) isolated by insulation films. Openings are made utilizing a single photoresist mask by etching the polycrystalline silicon layer and the underlying insulation film in one sequence. The polycrystalline silicon layers and diffused regions of the substrate exposed in the openings, are connected with a tungsten film (12) by selective deposition.
Ueda, Seiji. (1990). Method of making interconnects between polysilicon layers (U.S. Patent No. 4948756). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4948756
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile