The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 1990

Filed:

Feb. 26, 1988
Applicant:
Inventors:

Timothy G O'Shaughnessy, Norco, CA (US);

David K Chung, Lake Elsinore, CA (US);

Richard W Hull, Laguna Hills, CA (US);

Kenneth W Ouyang, Huntington Beach, CA (US);

Victor G Pierotti, Anaheim, CA (US);

Joseph A Souza, Costa Mesa, CA (US);

Assignee:

Western Digital Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307572 ; 307246 ; 307270 ; 307443 ; 307491 ; 307542 ;
Abstract

The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise. A dynamic clamp suppresses voltage spikes extending outside the voltage supply operating range. A bias circuit arrangement compensates for sheet resistivity of the integrated circuit chip. If the resistance value of the sheet drops below a prescribed value, the fixed current is limited so it cannot exceed its designed value.


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