The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 1990
Filed:
Feb. 13, 1989
Peter C Metz, Emmaus, PA (US);
Robert L Pritchett, Bath, PA (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.