The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 1990

Filed:

Feb. 21, 1989
Applicant:
Inventor:

Josephus M Van Laarhoven, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B44C / ; C03C / ; C23F / ;
U.S. Cl.
CPC ...
156643 ; 156644 ; 156646 ; 156648 ; 156651 ; 156656 ; 156657 ; 156662 ; 156668 ; 437 62 ; 437193 ; 437194 ;
Abstract

A method is described for providing insulating material on an electrically conductive level (1) of a substructure (10) forming part of an electronic device, which electrically conductive level has at least two spaced-apart electrically conductive regions (1a,1b). Insulating material (2,3) is provided over the electricaly conductive level (1) to a thickness insufficient for insulating material on adjacent conductive regions (1a,1b) to meet thereby leaving a recess (4) in the insulating material between the conductive regions (1a,1b). Next a planarising medium (5) is applied onto the insulating material (2,3) and etched so as to expose a top surface (3a) of the insulating material (2,3) thereby leaving planarising medium (5a) in the recess (4). The insulating material (2,3) is then etched anisotropically using the remaining planarising medium (5a,5b) as a mask so that the surface (11) of the electrically condutive level (1) is exposed. The etching of the insulating material ( 2,3) is controlled so that the insulating material is etched away just down to the bottom (50a) of the planarising medium (5a) in the recess (4) and the remaining planarising medium (5a,5b) is then removed so as to leave the surface of the substructure (10) between the electrically conductive regions (1a,1b) covered by a relatively flat layer (30) of insulating material. A further layer (6), for example of insulating mateirl, is then deposited onto the remaining relatively flat layer of insulating material.


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