Write control circuit for a high-speed memory device

Abstract

A built-in write control circuit of an IC memory receives first and second write enable signals that each have a duration equal to two operation cycles, the phase difference between these signals being equal to any odd number of operation cycles. The first and second write enable signals are converted into first and second write mode signals, respectively, each having a duration equal to one operation cycle, with the second write mode signal having a phase difference relative to the first write mode signal equal to the phase difference between the first and second write enable signals. A write pulse generator is included which receives a train of clock pulses having an interval equal to one operation cycle, and generates a train of write pulses in synchronism with the clock pulses. These write pulses are gated by each of the first and second write mode signals, and the resulting gated write signal is applied to sense amplifiers to control writing data into a memory array.