Improved pipelined processor with two stage decoder for exchanging

Abstract

A pipelined processor to improve the efficiency of conventional pipelined instruction processing including a two stage instruction decoder which converts sets of similar conventional instructions having the general formats: 'MOV: A R1 R2' and 'MOV: B R1 R2' where the letter fields A,B etc. indicate the direction of data transfer between the registers, R1, R2; into a single format instruction which can be processed by one microprogram. The first stage decoder processes one instruction intact and generates an intermediate code for the remaining format instruction. The second stage decoder utilizes the intermediate code to specify the direction of transfer by reversing the sequence of register numbers in the instruction not processed intact by the first stage. The resulting transfer instructions have the same format and thus require one, rather than two, microprograms for execution, making the pipelined processor more efficient.