The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 1990
Filed:
May. 01, 1987
John S Young, Scottsdale, AZ (US);
Peter Kruis, Glendale, AZ (US);
William D Blewitt, Phoenix, AZ (US);
AG Communication Systems Corporation, Phoenix, AZ (US);
Abstract
This circuit is a trunk type interface circuit which interfaces between duplicate copies of an ISDN system and T-carrier facilities. The circuit is controlled by a digital signal processor which has a 16-bit wide data bus. The digital signal processor is capable of supporting various Zero Byte Time Slot Interchange (ZBTSI) techniques. Also included is an administrative microprocessor which collects data concerning the operation of the trunk circuit and transmits this information to the ISDN system. The administrative microprocessor also receives information from currently unused data bits in the input bit stream from the ISDN system. The trunk circuit includes one receiver which collects and stores data transmitted by the ISDN system. Another receiver collects and stores data transmitted via the T-carrier facilities. The trunk circuit also includes two transmitters. One transmitter converts previously formatted data to T-carrier compatible data and transmits the data via the T-carrier facilities. the other transmitter converts reformatted data received from the T-carrier facility to data compatible with the ISDN format and transmit this data to the ISDN system. The memory of this circuit includes a dual port random access memory which provides for nearly simultaneous access by two separate input/output controllers.