The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 1990
Filed:
Sep. 16, 1988
Nobukazu Hosoya, Nara, JP;
Kazunori Nohara, Osaka, JP;
Yasuyuki Ikeguchi, Higashiosaka, JP;
Tooru Sasaki, Matsubara, JP;
Yoshichika Hirao, Neyagawa, JP;
Sanyo Electric Co., Ltd., Moriguchi, JP;
Abstract
A peak holding circuit comprises a capacitor for holding signal charges corresponding to a peak level of an input signal, and a current amplifier circuit comprising transistors connected in a triple darlington manner for supplying an output current corresponding to the held charges. An emitter of a transistor in the first stage out of the transistors connected in a darlington manner is connected to a collector of another transistor through which a collector cut-off current flows which is approximately equal to a collector cut-off current flowing through the transistor in the first stage. The other transistor has its emitter connected to ground. Therefore, the collector cut-off current flowing through the transistor in the first stage is cancelled, so that fluctuations in output current can be prevented even if a large reactive current is not allowed to flow through a transistor in the final stage out of the transistors connected in a darlington manner.