The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 1990
Filed:
Mar. 22, 1989
Kenneth J Stern, Austin, TX (US);
John A Beck, Austin, TX (US);
Crystal Semiconductor, Austin, TX (US);
Abstract
A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive data that is synchronized with a Write clock output therefrom synchronized with a Read clock. The data is written to the FIFO register (10) from a location determined by a Write pointer (12). The data is read out from the FIFO register (10) from a location determined by a Read pointer (14) which is clocked by a Read clock. The Read clock is synchronized with the Write clock by a phase lock loop (24). The phase lock loop (24) has a phase detector (26) which is operable to accrue phase error over intervals of 2.pi. radians such that the phase lock loop (24) virtually never loses lock as a result of phase jitter on the Write clock. The phase lock loop (24) has contained therein a digitally controlled linear oscillator (28) wherein the phase detector (26) provides a quantized output to incrementally step the digitally controlled oscillator (28) up or down in frequency to track the Write clock while attenuating jitter thereon.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile