The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 1990

Filed:

Nov. 24, 1989
Applicant:
Inventors:

Dean L Benjamin, Ventura, CA (US);

Wayne K Wong, Camarillo, CA (US);

Assignee:

Harris Corporation, Melbourne, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04M / ; H04M / ;
U.S. Cl.
CPC ...
379 29 ; 379 34 ; 379 21 ;
Abstract

Corruption of communication signals on a telephone line by the direct (low impedance) interfacing of test equiupment to the line is precluded by a protective interlock circuit, which prevents the test set from seizing the line if data traffic is present. The interlock circuit is coupled between the line circuit to be accessed and the test equipment, and includes a multiple band frequency detector, which monitors the line for signals lying within (in and out-of-audio) frequency bands. Should the detector identify any traffic within its sensitivity range (out of the audio band) during the interval of a timing pulse produced by the closure of a switch, the logic level applied to combinational logic will change state and prevent the generation of a test set enabling signal. The test set enabling signal is normally coupled to a `line-seize` transistor circuit within the test set, so that, without this enabling signal, the test set is effectively locked-out from the line and data cannot be corrupted. Should the frequency detector not have produced an out of audio band detection signal after the expiration of the timing pulse, the combinational logic circuit and an associated flip-flop generate an output signal for enabling the test equipment to seize the line. The flip-flop remains set and the logic level of the output signal is maintained until the line is no longer seized by the test equipment.


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