Static random access memory

Abstract

In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to a high level, a pulse generator generates a pulse signal in '1' level and with a given pulse width. In response to this pulse signal, a first MOS transistor is turned on to short paired bit lines. This pulse signal turns on second and third MOS transistors. Then, the potentials on the paired bit lines are pulled up to a power source potential. As a result, of the two bit lines, the bit line which has been set at a low potential immediately after data is written, is charged. A pulse extension/inverting circuit extends the pulse width of the pulse signal generated by a pulse generator by a given time period, and inverts a logical state of the pulse signal. During a period that the first MOS transistor shorts the bit lines to place the equal potentials on the bit lines, the pulse signal .phi.WRD output from the pulse extension/inverting circuit is kept in '0' level. During this period, therefore, the output data of two AND gates is '0' level irrespective of the sensed data from a read circuit and the supply of the sensed data from the read circuit to a data output circuit is stopped.