The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 1990
Filed:
May. 30, 1989
Jan Fandrianto, Los Gatos, CA (US);
Weitek Corporation, Sunnyvale, CA (US);
Abstract
An improved logic structure and a method for implementing the same to perform division and square-root operations for radix four and higher is disclosed. The divsion and square-root bits are generated by a non-restoring method with the partial remainder, partial radicand, quotient and root all in redundant form. The partial remainder/radicand is stored in a series of sum and carry registers. The upper bits from these registers are supplied to a carry look-ahead adder for conversion to non-redundant form. These upper bits are then used to select a next divisor or root from a prediction programmable logic array (PLA). The output of the prediction PLA is supplied to a quotient/root register and a divisor/root multiple selector. The output of the selector is supplied to a carry save adder which has its output provided back to the input of the partial remainder/radicand sum and carry registers. The system of the present invention allows both division and square root calculations to be done with the same hardware. The square-root algorithm requires an initial look-up PLA for determining the initial bits of the square-root. Logic is provided for coupling the output of this initial look-up PLA to the quotient/root register and divisor/root multiple select during the first few iterations.