The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 1990
Filed:
Oct. 02, 1989
Cleon Petty, Tempe, AZ (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
An single power supply ECL to TTL/CMOS translator is provided for converting a signal from differential ECL logic levels to TTL or CMOS compatible logic levels without introducing current spikes in the output signal during logic transitions. The differential ECL input signal is transformed into first and second differentially related signals having predetermined differential and single ended magnitudes. The first and second differentially related signals are then buffered and applied, as independent single ended signals, to first and second conduction paths controlling the first and second switching circuits in an output stage, respectively. The relative magnitudes of the first and second differentially related signals at the output of the buffer induce unequal slew rates at the input of the first and second conduction paths such that the first switching circuit is turned off before the second switching circuit is turn on thereby preventing simultaneous conduction and the associated undesirable current spikes flowing therethrough.