The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 1990
Filed:
May. 22, 1989
Arthur J Edwards, Hoffman Estates, IL (US);
Kirk Sievers, Roselle, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Semiconductor device protection circuit (10) provides increased power dissipation (current) limits for FET (11) when lower FET temperatures exist. The FET drain to source voltage (V.sub.DS) is monitored to provide a current sense signal (54). When the current sense signal exceeds a predetermined reference limit signal (V.sub.REF,55), a control circuit (23, 32) reduces current (power dissipation) in the FET. Circuitry (24) provides the reference limit signal (V.sub.REF) with a predetermined temperature variation as a function of the sensed temperature of the FET whereby for low device temperatures higher power dissipation (current) limits for the FET are provided. An additional control circuit (21, 30) provides short circuit overcurrent protection by reducing current in the FET when sensed FET current exceeds a predetermined limit. A delay circuit (39) inhibits operation of at least the control circuit (20, 32) until a predetermined time (t.sub.1) after the FET is turned on.