The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 1990

Filed:

Nov. 23, 1988
Applicant:
Inventors:

Larry J Kendall, San Jose, CA (US);

Andrew Palfreyman, Sunnyvale, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371-55 ; 371 28 ;
Abstract

An error measurement and reduction method, including the steps of inducing a high error rate in a mass storage device memory system to determine rapidly and independently the optimal pattern sensitivity, pulse pairing, and window centering error parameters for the system. In a preferred embodiment, the system error rate is then reduced by setting at least one, and preferably all three, of the error parameters to its optimal value. The inventive system includes means for performing the inventive method, and preferably includes computer-controllable means for independently adjusting the pattern sensitivity and pulse pairing error parameters associated with each read/write head of the system, and for adjusting the window centering error parameter associated with the system. The inventive method and system exploit the mutual orthogonality (with respect to overall system error rate) of the pattern sensitivity pulse pairing, and window centering error parameters, which mutual orthogonality exists when the system reads selected test patterns.


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