The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 1990
Filed:
Oct. 31, 1988
Yeong-Chang Lien, Armonk, NY (US);
Roch A Guerin, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In a data communication network the routing of data items from a group of eight source processors to a group of eight destination processors is controlled by code values assigned to each of the data values. The data items to be routed are bit-serial binary signals. These are encoded by the source processor using a pair of code values, one for each value of a bit of the binary signal. The eight source processors each encode eight bit-serial signals using respectively different code tables. The code tables are generated as different permutations of a basic code set. Each code table has the property that any additive combination of encoded values for all of the data items in a group produces a unique sum. The eight encoded values produced by each processor are summed to produce a set of analog channel symbols that are transmitted over an analog channel to a central switch fabric. In the switch fabric, the channel symbols are partially decoded to recover the encoded data values. The data values are regrouped according to their destination processors and summed to produce further sets of channel symbols which are transmitted to the destination processors. At the destination processors, the data values are completely decoded and assigned to separate input terminals of the destination processors based on their source processor.