The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 1990

Filed:

Jan. 19, 1989
Applicant:
Inventor:

Hideki Ueda, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ; H01Q / ;
U.S. Cl.
CPC ...
455113 ; 455117 ; 455119 ; 455115 ; 331 10 ; 331 16 ; 331175 ; 332127 ; 332128 ;
Abstract

A transmitter includes a phase-locked loop (PLL) circuit whose output is frequency modulated with a modulation signal. The modulated signal is amplified by an amplifier which is turned on only during a signal transmission of the transmitter. At a time when the amplifier is turned, the output frequency of PLL circuit fluctuates. To depress this frequency fluctuation, the transmitter includes a frequency fluctuation depressing (FFD) circuit. Upon the turning-on of the amplifier, FFD circuit applies a voltage change to the modulation signal so that the frequency fluctuation is depressed.


Find Patent Forward Citations

Ueda, Hideki. (1990). Transmitter having pll circuit (U.S. Patent No. 4932073). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4932073

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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