Semiconductor memory device which can suppress operation error due to

Abstract

A row address signal is supplied to a row address input buffer, and a column address signal is supplied to a column address input buffer. The row address signal supplied to the row address input buffer is then supplied to a row main decoder, through a row address predecoder, the column address signal supplied to the column address input buffer being supplied to a column address predecoder. An output from the column address predecoder is supplied to a filter or delay circuit, and an output signal from the filter or delay circuit is supplied to a column main decoder. One memory cell in a memory cell array is selected in response to decode outputs from the row main decoder and the column main decoder, and readout data of the selected memory cell is amplified by a sense amplifier. An output from the sense amplifier is output through a data output circuit and a data output buffer. An erroneous detected signal of the column address buffer, arising from power supply noise generated when an output from the data output buffer is inverted, is eliminated or reduced by the filter or delay circuit.