Static semiconductor memory with section and block sense amplifiers

Abstract

A static semiconductor memory comprises a word line, a memory cell array divided into a plurality of blocks in an extending direction of the word line, each block including a plurality of sections each of which includes a plurality of static memory cells, a controller, a section data line provided for each section, first sense amplifiers, a block data line provided for each block, second sense amplifiers, a main data line and a latch circuit for latching data on the main data line. The controller selects an arbitrary section in the memory cell array at the time of data readout and controls the reading of data from memory cells included in the selected section. The section data line is supplied with data read out from the memory cells. The first sense amplifiers, coupled at their input terminals to the section data line, are activated only when their associated section is selected. The individual first sense amplifiers in the same block have their output terminals commonly coupled to the block data line. Each second sense amplifier, coupled at its input terminal to the associated block data line, is activated only when the sections belonging to that block are selected. The second sense amplifiers have their output terminals commonly coupled to the main data line.