The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 1990
Filed:
Jan. 30, 1989
Applicant:
Inventors:
Danh Le Ngoc, Saratoga, CA (US);
John R Mick, Los Altos Hills, CA (US);
Assignee:
Integrated Device Technology, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364736 ;
Abstract
For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ('A'), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and 'delay' the parameter represented by the state of signals externally developed on a 'DA' bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for 'bit-reverse order' addressing; and a unit for 'rounding off' certain results.