The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 1990
Filed:
Jan. 10, 1989
Roger J Stierman, Richardson, TX (US);
Robert J Lessard, Garland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.