The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 1990

Filed:

Aug. 29, 1988
Applicant:
Inventors:

Michael Danilenko, West St. Paul, MN (US);

Clarence W Dekarske, St. Paul Park, MN (US);

John E Larson, Eagan, MN (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518901 ; 365 49 ; 364200 ;
Abstract

A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.


Find Patent Forward Citations

Danilenko, Michael. (1990). Dual cache ram for rapid invalidation (U.S. Patent No. 4930106). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4930106

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…