The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 1990
Filed:
Jun. 05, 1989
Michael D Jack, Goleta, CA (US);
George R Chapman, Santa Barbara, CA (US);
Michael Ray, Goleta, CA (US);
Santa Barbara Research Center, Goleta, CA (US);
Abstract
A method of forming in a semiconductor material a region having a different chemical composition or a different concentration than a chemical composition or concentration of material surrounding the region. The method includes an initial step of providing a substantially single crystalline body of material, such as an epitaxial layer 10 of HgCdTe. Another step forms a cap layer 12 over a surface of the body, the layer having a thickness T. The cap layer 12 is comprised of a layer of polycrystalline material, such as CdTe, or is comprised of a layer of an organic material, an amorphous dielectric or a single-crystalline layer. A further step implants a selected chemical species through an upper surface of the cap, the species being implanted to a depth such that substantially no implant damage is sustained by the underlying body. In p-n junction formation the species is selected to form a region having an opposite type of electrical conductivity than the conductivity of the layer 10. A further step diffuses during a thermal anneal the implanted species from the cap layer down into the underlying layer to form a region therein having a different chemical composition or concentration than the chemical composition or concentration of the material surrounding the region. The method is also shown to be suitable for bipolar and JFET transistor fabrication in Group II-VI and Group III-V materials.