Bicmos write-recovery circuit

Abstract

A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.