The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 1990

Filed:

Feb. 17, 1988
Applicant:
Inventors:

Stamatis Vassiliadis, Vestal, NY (US);

Michael Putrino, Endicott, NY (US);

Ann E Huffman, Johnson City, NY (US);

Brice J Feal, Endicott, NY (US);

Gerald G Pechanek, Endwell, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36471509 ; 3647365 ;
Abstract

The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.


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