The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 1990
Filed:
Aug. 03, 1988
Robert H Lee, Fullerton, CA (US);
Teledyne Inet, Torrance, CA (US);
Abstract
A polyphase AC current limiting circuit, which incorporates improvements in control methods and circuitry that operate to avoid high rates of current change which occur upon initiation of a branch load fault and when the branch load fault is suddenly cleared. This 'soft' start and 'soft' load-off characteristic, reduces the voltage transients imposed on the AC power source and bus to relative insignificance compared with the voltage transients imposed by prior art current limiting circuits. The invention AC current limiting circuit comprises a high impedance circuit connected in parallel with a low impedance circuit, a load-off circuit connected in shunt with the device output power lines, and a control means for controlling the switching devices. When a branch load fault is sensed, the control means turns off the switches in the low impedance circuit through which normal current flows, and turns on the switches in the high impedance circuit, starting phased back, so that the initial current step is typically 100 percent of rated load current. Within a few cycles, the switches are phased to full on and the maximum current is limited by an inductor in series with the switches in the high impedance circuit. When the load fault is suddenly cleared and current drops to zero, the load-off circuit is energized and current continues to flow at graduated lower levels until the circuit is switched off. In the event that the load fault does not clear, the switches in the high impedance circuit are turned off, stopping current flow and a trip signal is transmitted to trip open an external input circuit breaker.